# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.

[options]

# wordswap swaps labels if the pin is on the right side an looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...

wordswap=yes
rotate_labels=yes
#generate_pinseq=yes
pinwidthvertical=500
pinwidthhorizontal=500
sym_width=6000
sort_labels=no

[geda_attr]

# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add

version=20101118 1
name=LPC1768
device=IC
refdes=U1
description=32-bit ARM Cortex-M3 microcontroller GPIOs
numslots=0
footprint=LQFP100_10
documentation=""
author=Siddharth Sharma
dist-license=GPL 
use-license=public domain

[pins]

# tabseparated list of pin descriptions
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the Vcc or GND name
# label represents the pinlabel.
#	negation lines can be added with _Q_
#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label
#-----------------------------------------------------
46		io	line	l		P0[0] (RD1/TXD3/SDA1)
47		io	line	l		P0[1] (TD1/RXD3/SCL1)
98		io	line	l		P0[2] (TXD0/AD0[7])
99		io	line	l		P0[3] (RXD0/AD0[6])
81		io	line	l		P0[4] (I2SRXCLK/RD2/CAP2[0])
80		io	line	l		P0[5] (I2SRXWS/TD2/CAP2[1])
79		io	line	l		P0[6] (I2SRXSDA/SSEL1/MAT2[0])
78		io	line	l		P0[7] (I2STXCLK/SCK1/MAT2[1])
77		io	line	l		P0[8] (I2STXWS/MISO1/MAT2[2])
76		io	line	l		P0[9] (I2STXSDA/MOSI1/MAT2[3])
48		io	line	l		P0[10] (TXD2/SDA2/MAT3[0])
49		io	line	l		P0[11] (RXD2/SCL2/MAT3[1])
62		io	line	l		P0[15] (TXD1/SCK0/SCK)
63		io	line	l		P0[16] (RXD1/SSEL0/SSEL)
61		io	line	l		P0[17] (CTS1/MISO0/MISO)
60		io	line	l		P0[18] (DCD1/MOSI0/MOSI)
59		io	line	l		P0[19] (DSR1/SDA1)
58		io	line	l		P0[20] (DTR1/SCL1)
57		io	line	l		P0[21] (RI1/RD1)
56		io	line	l		P0[22] (RTS1/TD1)
9		io	line	l		P0[23] (AD0[0]/I2SRXCLK/CAP3[0])
8		io	line	l		P0[24] (AD0[1]/I2SRXWS/CAP3[1])
7		io	line	l		P0[25] (AD0[2]/I2SRXSDA/TXD3)
6		io	line	l		P0[26] (AD0[3]/AOUT/RXD3)
25		io	line	l		P0[27] (SDA0/USBSDA)
24		io	line	l		P0[28] (SCL0/USBSCL)
29		io	line	l		P0[29] (USBD+)
30		io	line	l		P0[30] (USBD−)
95		io	line	r		P1[0] (ENETTXD0)
94		io	line	r		P1[1] (ENETTXD1)
93		io	line	r		P1[4] (ENETTXEN)
92		io	line	r		P1[8] (ENETCRS)
91		io	line	r		P1[9] (ENETRXD0)
90		io	line	r		P1[10] (ENETRXD1)
89		io	line	r		P1[14] (ENETRXER)
88		io	line	r		P1[15] (ENETREFCLK)
87		io	line	r		P1[16] (ENETMDC)
86		io	line	r		P1[17] (ENETMDIO)
32		io	line	r		P1[18] (USBUPLED/PWM1[1]/CAP1[0])
33		io	line	r		P1[19] (MCOA0/\_USBPPWR\_/CAP1[1])
34		io	line	r		P1[20] (MCI0/PWM1[2]/SCK0)
35		io	line	r		P1[21] (\_MCABORT\_/PWM1[3]/SSEL0)
36		io	line	r		P1[22] (MCOB0/USBPWRD/MAT1[0])
37		io	line	r		P1[23] (MCI1/PWM1[4]/MISO0)
38		io	line	r		P1[24] (MCI2/PWM1[5]/MOSI0)
39		io	line	r		P1[25] (MCOA1/MAT1[1])
40		io	line	r		P1[26] (MCOB1/PWM1[6]/CAP0[0])
43		io	line	r		P1[27] (CLKOUT/\_USBOVRCR\_/CAP0[1])
44		io	line	r		P1[28] (MCOA2/PCAP1[0]/MAT0[0])
45		io	line	r		P1[29] (MCOB2/PCAP1[1]/MAT0[1])
21		io	line	r		P1[30] (VBUS/AD0[4])
20		io	line	r		P1[31] (SCK1/AD0[5])
75		io	line	r		P2[0] (PWM1[1]/TXD1)
74		io	line	r		P2[1] (PWM1[2]/RXD1)
73		io	line	r		P2[2] (PWM1[3]/CTS1/TRACEDATA[3])
70		io	line	r		P2[3] (PWM1[4]/DCD1/TRACEDATA[2])
69		io	line	r		P2[4] (PWM1[5]/DSR1/TRACEDATA[1])
68		io	line	r		P2[5] (PWM1[6]/DTR1/TRACEDATA[0])
67		io	line	r		P2[6] (PCAP1[0]/RI1/TRACECLK)
66		io	line	r		P2[7] (RD2/RTS1)
65		io	line	r		P2[8] (TD2/TXD2)
64		io	line	r		P2[9] (USBCONNECT/RXD2)
53		io	line	r		P2[10] (\_EINT0\_/NMI)
52		io	line	r		P2[11] (\_EINT1\_/I2STXCLK)
51		io	line	r		P2[12] (\_EINT2\_/I2STXWS)
50		io	line	r		P2[13] (\_EINT3\_/I2STXSDA)
27		io	line	l		P3[25] (MAT0[0]/PWM1[2])
26		io	line	l		P3[26] (STCLK/MAT0[1]/PWM1[3])
82		io	line	l		P4[28] (RXMCLK/MAT2[0]/TXD3)
85		io	line	l		P4[29] (TXMCLK/MAT2[1]/RXD3)